{"id":175,"date":"2017-04-24T17:33:01","date_gmt":"2017-04-24T08:33:01","guid":{"rendered":"http:\/\/tamatoyaku.com\/b\/?p=175"},"modified":"2017-04-24T17:33:01","modified_gmt":"2017-04-24T08:33:01","slug":"175","status":"publish","type":"post","link":"https:\/\/p-0.me\/b\/p\/175\/","title":{"rendered":"ModelSim-Altera\u3067FPGA\u5165\u9580(2)"},"content":{"rendered":"

\u524d\u56de<\/a>\u306b\u5f15\u304d\u7d9a\u304d\uff0c\u4eca\u56de\u306f\u534a\u52a0\u7b97\u5668(half adder)\u30922\u3064\u4f7f\u3063\u3066\uff0c\u5168\u52a0\u7b97\u5668(full adder)\u3092\u4f5c\u6210\u3059\u308b\uff0e
\n
\n\u4eca\u56de\u306ffaddr\u3068\u3044\u3046\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3092\u4f5c\u6210\u3059\u308b\uff0e
\nfaddr\u306e\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u30d5\u30a9\u30eb\u30c0\u306b\u524d\u56de\u4f5c\u6210\u3057\u305fhaddr.v\u3092\u30b3\u30d4\u30fc\u3057\uff0c[Project]->[Add\/Remove Files in Project]\u304b\u3089faddr\u306e\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306bhaddr.v\u3092\u8ffd\u52a0\u3059\u308b\uff0e
\n 
\n[File]->[New]\u304b\u3089[Design Files]\u30bf\u30d6\u306eVerilog HDL File\u3092\u9078\u629e\uff0cfaddr.v\u3068\u3057\u3066\u4fdd\u5b58\u3059\u308b\uff0e
\nfaddr.v\u306e\u5185\u5bb9\u306f\u4ee5\u4e0b\u306e\u3088\u3046\u306b\u3059\u308b\uff0e<\/p>\n

module faddr(clk,in_A,in_B,cin,out,cout);\ninput clk,in_A,in_B,cin;\noutput reg out,cout;\nwire out1,cout1;\nwire out2,cout2;\nhaddr haddr1(clk,in_A,in_B,out1,cout1);\nhaddr haddr2(clk,out1,cin,out2,cout2);\nalways @(posedge clk)begin\nout<=out2;\ncout<=cout1|cout2;\nend\nendmodule<\/pre>\n
 
\n[Processing]->[Start]-[Start Analysis & Synthesis]\u3067\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u884c\u3046\uff0e
\n\u30b3\u30f3\u30d1\u30a4\u30eb\u304c\u901a\u3063\u305f\u3089,[Tools]->[Run Simulation Tools]->[RTL Simulation]\u3067\u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u3092\u8d77\u52d5\uff0e
\n\u524d\u56de\u3068\u540c\u69d8\u306b\uff0c\u5165\u529b\u6ce2\u5f62\u3092\u4f5c\u6210\u3059\u308b\uff0e
\n[Library]\u30bf\u30d6\u3092work\u3092\u5c55\u958b\u3057\uff0cfaddr\u3092\u53f3\u30af\u30ea\u30c3\u30af\u3057\u3066Create Wave\u3092\u9078\u629e\uff0e
\n[Wave]\u30d5\u30a9\u30fc\u30e0\u306b\u5404\u4fe1\u53f7\u304c\u8868\u793a\u3055\u308c\u308b\u306e\u3067\uff0c\u5165\u529b\u95a2\u4fc2\u306e\u307f\u9069\u5f53\u306b\u30bb\u30c3\u30c8\uff0e
\n\"\"
\n\u4eca\u56de\u306f\u3053\u306e\u3088\u3046\u306b\u3057\u305f.
\n\u771f\u7406\u5024\u8868\u306e\u5168\u30d1\u30bf\u30fc\u30f3\u3092\u7db2\u7f85\u3059\u308b\u305f\u3081\u306b\uff0cin_A\u306e\u5468\u671f\u3092400[ns],in_B\u3092200[ns]\uff0ccin\u3092100[ns]\u3068\u3057\u305f.
\n\u306a\u304a,clk\u306f\u5468\u671f\u77ed\u3081\u306b\u3057\u3066\uff0c\u7d50\u679c\u304c\u5373\u6642\u53cd\u6620\u3055\u308c\u308b\u3088\u3046\u306b\u3057\u3066\u3044\u308b.
\n\"\"
\n\u524d\u56de\u3068\u540c\u69d8\uff0c[File]->[Export]->[Waveform]\u304b\u3089Verilog Testbench\u3092\u9078\u629e\u3057\uff0ctb.v\u3068\u3057\u3066\u4fdd\u5b58\u3059\u308b\uff0e
\n\u7d42\u308f\u3063\u305f\u3089ModelSim\u3092\u9589\u3058\u308b\uff0e
\n 
\n[Project]->[Add\/Remove Files in Project]\u304b\u3089tb.v\u3092\u8ffd\u52a0\u3059\u308b\uff0e
\ntb.v\u3092\u958b\u304d\uff0c\u300cwire reg \u5909\u6570\u540d;\u300d\u3092\u300cwire \u5909\u6570\u540d;\u300d\u306b\u66f8\u304d\u63db\u3048\u308b\uff0e
\n\u305d\u306e\u5f8c\uff0c[Processing]->[Start]-[Start Analysis & Synthesis]\u3067\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u884c\u3046\uff0e
\n\"\"
\n[Assignments]->[Settings…]\u3092\u958b\u304d\uff0c[EDA Tool Settings]->[Simulation]\u306e\u4e2d\u306b\u3042\u308bNativeLink Settings\u3092\u8a2d\u5b9a\u3059\u308b\uff0e
\n\u8a73\u3057\u304f\u306f\u524d\u56de\u53c2\u7167\uff0e
\n\u518d\u3073ModelSim\u3092\u8d77\u52d5\u3059\u308b\u3068\uff0c\u3053\u3046\u306a\u3063\u305f.\u305f\u3076\u3093\u6b63\u3057\u3044\u306f\u305a\uff0e
\n\"\"
\n\u3061\u3087\u304f\u3061\u3087\u304f\u5909\u306a\u3075\u3046\u306b\u306a\u3063\u3066\u308b\u306e\u306f\uff0chaddr2\u306e\u5165\u529b\u306fhaddr1\u306e\u5165\u529b\u306a\u306e\u306b\u540c\u3058clk\u3092\u4f7f\u3063\u3066\u308b\u304b\u3089\u304b\u306a.
\n\u30af\u30ed\u30c3\u30af\u3092\u7d30\u304b\u304f\u3057\u305f\u3089\u5909\u306a\u3068\u3053\u308d\u306e\u5e45\u304c\u72ed\u307e\u3063\u305f\u306e\u3067\uff0c\u305f\u3076\u3093\u305d\u3046\u3067\u3057\u3087\u3046\uff0e
\n\"\"
\n\u306a\u304a,\u30ad\u30e3\u30ea\u30fc\u4e88\u6e2c\u3068\u304b\u306f\u9762\u5012\u306a\u306e\u3067\u884c\u308f\u306a\u3044\uff0e<\/p>\n","protected":false},"excerpt":{"rendered":"
\u524d\u56de\u306b\u5f15\u304d\u7d9a\u304d\uff0c\u4eca\u56de\u306f\u534a\u52a0\u7b97\u5668(half adder)\u30922\u3064\u4f7f\u3063\u3066\uff0c\u5168\u52a0\u7b97\u5668(full adder)\u3092\u4f5c\u6210\u3059\u308b\uff0e<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[5],"tags":[],"class_list":["post-175","post","type-post","status-publish","format-standard","hentry","category-tech"],"_links":{"self":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts\/175","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/comments?post=175"}],"version-history":[{"count":0,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts\/175\/revisions"}],"wp:attachment":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/media?parent=175"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/categories?post=175"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/tags?post=175"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}