{"id":140,"date":"2017-04-24T00:31:04","date_gmt":"2017-04-23T15:31:04","guid":{"rendered":"http:\/\/tamatoyaku.com\/b\/?p=140"},"modified":"2017-04-24T00:31:04","modified_gmt":"2017-04-23T15:31:04","slug":"140","status":"publish","type":"post","link":"https:\/\/p-0.me\/b\/p\/140\/","title":{"rendered":"ModelSim-Altera\u3067FPGA\u5165\u9580(1)"},"content":{"rendered":"

\u7814\u7a76\u3067\u4f7f\u3046\u53ef\u80fd\u6027\u304c\u3042\u308b\u304b\u3089FPGA\u3092\u3084\u308a\u59cb\u3081\u308b\uff0e
\n\u8a00\u8a9e\u306f\u3068\u308a\u3042\u3048\u305aVerilog.\u8a55\u4fa1\u30dc\u30fc\u30c9\u306f\u305d\u306e\u3046\u3061DE10 nano\u3092\u8cb7\u3046\u304b\u3082\u3057\u308c\u306a\u3044\uff0e
\n\u306a\u304a,\u3053\u3053\u306b\u3042\u308b\u60c5\u5831\u306f2017\u5e744\u670824\u65e5\u6642\u70b9\u306e\u3082\u306e\u3067\u3042\u308a,\u53e4\u304f\u306a\u3063\u3066\u4f7f\u3048\u306a\u304f\u306a\u308b\u53ef\u80fd\u6027\u304c\u9ad8\u3044\u306e\u3067\u6ce8\u610f\uff0e
\n 
\n
\n1.Quartus prime\u306e\u30a4\u30f3\u30b9\u30c8\u30fc\u30eb<\/strong>
\n\u3053\u306e\u30da\u30fc\u30b8<\/a>\u304b\u3089\u30c0\u30a6\u30f3\u30ed\u30fc\u30c9\uff0c\u30a4\u30f3\u30b9\u30c8\u30fc\u30eb\u3092\u884c\u3046\uff0e
\nQuartus Prime\u3068ModelSim,Cyclone V device support\u3092\u5165\u308c\u308c\u3070\u5927\u4e08\u592b\u306a\u306f\u305a\uff0e
\n\u8a73\u7d30\u306f\u5272\u611b\uff0e
\n 
\n2.\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306e\u4f5c\u6210<\/strong>
\nQuartus Prime\u3092\u958b\u304f\uff0e
\n\"\"
\n[File]->[New Project Wizard…]\u304b\u3089\u65b0\u3057\u3044\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u3092\u4f5c\u308b\uff0e
\n\"\"
\n\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306e\u5834\u6240\u3068\u540d\u524d\u3092\u6c7a\u3081\u308b\uff0e
\n\"\"
\n\u4ee5\u5f8c\u3057\u3070\u3089\u304fNext\u9023\u6253\uff0e
\n\"\" \"\" \"\"
\nSimulation\u3092ModelSim-Altera\u306b\u3057\u3066,Format(s)\u3092Verilog\u306b\u3059\u308b
\n\"\"
\nFinish\u3092\u62bc\u3059\uff0e
\n\"\"
\n 
\n3.\u30bd\u30fc\u30b9\u30d5\u30a1\u30a4\u30eb\u306e\u4f5c\u6210<\/strong>
\n[File]->[New]\u304b\u3089[Design Files]->[Verilog HDL File]\u3067Verilog\u30d5\u30a1\u30a4\u30eb\u3092\u4f5c\u6210\u3059\u308b\uff0e
\n\"\"
\n\u4eca\u56de\u306f\u4f8b\u3068\u3057\u3066\u534a\u52a0\u7b97\u5668\u3092\u4f5c\u6210\u3059\u308b\uff0e<\/p>\n

module haddr(clk,in_A,in_B,out,cout);\noutput reg out,cout;\ninput clk,in_A,in_B;\nalways @(posedge clk)begin\nout<=in_A ^ in_B;\ncout<=in_A & in_B;\nend\nendmodule<\/pre>\n
\"\"
\n\u4f5c\u6210\u3057\u305f\u3089haddr.v\u3068\u3057\u3066\u4fdd\u5b58\u3059\u308b\uff0e
\n\u306a\u304a,\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u540d\u3068\u30d5\u30a1\u30a4\u30eb\u540d\u3092\u4e00\u81f4\u3055\u305b\u306a\u3044\u5834\u5408\u306f\uff0c\u305d\u306e\u30d5\u30a1\u30a4\u30eb\u3092Top Level\u306b\u8a2d\u5b9a\u3059\u308b\u5fc5\u8981\u304c\u3042\u308b\uff0e
\n 
\n4.\u30b3\u30f3\u30d1\u30a4\u30eb<\/strong>
\n[Processing]->[Start]->[Start Analysis & Synthesis]\u3067\u30b3\u30f3\u30d1\u30a4\u30eb\u3092\u884c\u3046\uff0e
\n\"\"
\n 
\n5.\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u4f5c\u6210<\/strong>
\n[Tools]->[Options]->[General]->[EDA Tool Options]\u304b\u3089ModelSim-Altera\u306b\u30d1\u30b9\u3092\u8a2d\u5b9a\u3059\u308b\uff0e
\n\u306a\u304a,\u6700\u5f8c\u306b\\\u3092\u5165\u308c\u306a\u3044\u3068\u30a8\u30e9\u30fc\u304c\u767a\u751f\u3059\u308b\u3089\u3057\u3044\uff0e
\n\"\"
\n[Tools]->[Run Simulation Tools]->[RTL Simulation]\u3067\u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u3092\u8d77\u52d5\u3059\u308b\uff0e
\n\"\"
\n[Library]\u30bf\u30d6\u304b\u3089work\u3092\u5c55\u958b\u3057\uff0chaddr\u3092\u53f3\u30af\u30ea\u30c3\u30af\u3057[Create Wave]\u3092\u30af\u30ea\u30c3\u30af
\n\"\"
\nWave\u30bf\u30d6\u306b\u4fe1\u53f7\u304c\u8868\u793a\u3055\u308c\u308b\u306e\u3067,\u5404\u5165\u529b\u4fe1\u53f7\u3092\u4f5c\u6210\u3059\u308b\uff0e
\n\"\"
\n\u5404\u5165\u529b\u4fe1\u53f7\u306b\u5bfe\u3057\u3066\u53f3\u30af\u30ea\u30c3\u30af,[Edit]->[Wave Editor]->[Create\/Modify Waveform]\u3092\u30af\u30ea\u30c3\u30af\uff0e
\n\"\"
\n\u5404\u5165\u529b\u4fe1\u53f7\u3092\u9069\u5f53\u306b\u4f5c\u6210\u3059\u308b\uff0e
\n\u4eca\u56de\u306fclk\u306e\u5468\u671f\u3092\u77ed\u304f\u3057\u5e38\u306b\u30c7\u30fc\u30bf\u3092\u66f4\u65b0\uff0cin_A\u306e\u5468\u671f\u3092in_B\u306e2\u500d\u306b\u3059\u308b\u3053\u3068\u306700,01,10,11\u306e4\u30d1\u30bf\u30fc\u30f3\u3092\u7db2\u7f85\u3067\u304d\u308b\u3088\u3046\u306b\u8a2d\u5b9a\u3059\u308b\uff0e
\n\"\"
\n\"\"
\n\"\"
\n\u8a2d\u5b9a\u3057\u7d42\u308f\u308b\u3068\u3053\u306e\u3088\u3046\u306b\u306a\u308b\uff0e
\n\"\"
\n[File]->[Export]->[Waveform…]\u304b\u3089Waveform\u3092\u4fdd\u5b58\u3059\u308b\uff0e
\n\"\"
\n\u4fdd\u5b58\u3057\u305f\u3089ModelSim\u3092\u9589\u3058\u308b\uff0e
\n 
\n6.\u30c6\u30b9\u30c8\u30d9\u30f3\u30c1\u306e\u8a2d\u5b9a<\/strong>
\n[Assignments]->[Settings…]->[EDA Tool Settings]->[Simulation]\u304b\u3089NativeLink settings\u306eConpile test bench\u3092\u30af\u30ea\u30c3\u30af\uff0e
\n\"\"
\nNew\u3092\u30af\u30ea\u30c3\u30af
\n\"\"
\nTest bench name\u306btb\u3068\u5165\u529b\u3059\u308b\uff0e
\nFile name\u304b\u3089\u4f5c\u88fd\u3057\u305ftb.v\u3092\u9078\u629e\u3057\uff0cAdd\u3092\u30af\u30ea\u30c3\u30af\uff0e
\n\"\"
\n\u8a2d\u5b9a\u95a2\u4fc2\u3092OK\u62bc\u3057\u3066\u5168\u90e8\u9589\u3058\u308b\uff0e
\n[Project]->[Add\/Remove Files in Project…]\u304b\u3089tb.v\u3092\u30d7\u30ed\u30b8\u30a7\u30af\u30c8\u306b\u8ffd\u52a0\u3059\u308b\uff0e
\n\"\"
\n[Processing]->[Start]->[Start Analysis & Synthesis]\u3067\u30b3\u30f3\u30d1\u30a4\u30eb\u3059\u308b\u3068\uff0c\u30a8\u30e9\u30fc\u304c\u51fa\u308b\uff0e
\n\"\"
\n\u30a8\u30e9\u30fc\u30e1\u30c3\u30bb\u30fc\u30b8\u3092\u30af\u30ea\u30c3\u30af\u3059\u308b\u3068tb.v\u304c\u958b\u304f\u306e\u3067\uff0cwire reg out\u3068wire reg cout\u3092\u305d\u308c\u305e\u308cwire out\u3068wire cout\u306b\u7f6e\u304d\u63db\u3048\u308b\uff0e
\n\u306a\u305c\u81ea\u52d5\u751f\u6210\u3067\u300cwire reg \u5909\u6570\u540d;\u300d\u3068\u3044\u3046\u6587\u304c\u751f\u6210\u3055\u308c\u308b\u306e\u304b\u306f\u4e0d\u660e\uff0e\u3067\u3082\u300cwire \u5909\u6570\u540d;\u300d\u306b\u3059\u308b\u3068\u76f4\u308b\uff0e\u4e0d\u601d\u8b70\uff0e
\n\"\"
\n\u4fdd\u5b58\u5f8c\uff0c\u518d\u3073[Processing]->[Start]->[Start Analysis & Synthesis]\u3067\u30b3\u30f3\u30d1\u30a4\u30eb\u3059\u308b\uff0e\u304a\u305d\u3089\u304f\u6210\u529f\u3059\u308b\uff0e
\n\"\"
\n 
\n7.\u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3<\/strong>
\n[Tools]->[Run Simulation Tools]->[RTL Simulation]\u3067\u30b7\u30df\u30e5\u30ec\u30fc\u30bf\u3092\u8d77\u52d5
\n\"\"
\n\u30a8\u30c7\u30a3\u30bf\u3092\u6d88\u3057\u3066Wave\u30bf\u30d6\u306b\u5207\u308a\u66ff\u3048\u308b\uff0e
\n\"\"
\n\u6700\u521d\u306f\u5e73\u5766\u306a\u4fe1\u53f7\u3057\u304b\u898b\u3048\u306a\u3044\u304c\uff0c\u3053\u308c\u306f\u7e2e\u5c3a\u304c\u5408\u3063\u3066\u3044\u306a\u3044\u305f\u3081\uff0e
\n\u866b\u773c\u93e1\u30de\u30fc\u30af\u3067\u7e2e\u5c3a\u3092\u8abf\u6574\u3057\uff0c\u4fe1\u53f7\u3092\u5de6\u7aef\u306e0[ns]\u3042\u305f\u308a\u3092\u898b\u308b\uff0e
\n\"\"
\n\u4fe1\u53f7\u306e\u9806\u756a\u304c\u6c17\u306b\u5165\u3089\u306a\u3044\u306e\u3067\uff0c\u30c9\u30e9\u30c3\u30b0\u3057\u3066\u5165\u308c\u66ff\u3048\u308b\uff0e
\n\"\"
\n\u534a\u52a0\u7b97\u5668\u3068\u3057\u3066\u305f\u3076\u3093\u6b63\u3057\u3044\u51fa\u529b\u306a\u306e\u3067\uff0c\u3053\u308c\u3067OK
\n 
\n8.\u304a\u308f\u308a\u306b<\/strong>
\n\u3053\u308c\u3067\u534a\u52a0\u7b97\u5668\u3068\u3057\u3066\u306e\u30b7\u30df\u30e5\u30ec\u30fc\u30b7\u30e7\u30f3\u7d42\u308f\u308a\uff0e
\n\u6b21\u306f\u534a\u52a0\u7b97\u5668\u3092\u30e2\u30b8\u30e5\u30fc\u30eb\u3068\u3057\u3066\u5168\u52a0\u7b97\u5668\u3092\u4f5c\u6210\u3057\u305f\u3044\uff0e
\n\u305d\u308c\u304c\u7d42\u308f\u3063\u305f\u3089\u30ab\u30a6\u30f3\u30bf\u3068\u304b\u304b\u306a.<\/p>\n","protected":false},"excerpt":{"rendered":"
\u7814\u7a76\u3067\u4f7f\u3046\u53ef\u80fd\u6027\u304c\u3042\u308b\u304b\u3089FPGA\u3092\u3084\u308a\u59cb\u3081\u308b\uff0e \u8a00\u8a9e\u306f\u3068\u308a\u3042\u3048\u305aVerilog.\u8a55\u4fa1\u30dc\u30fc\u30c9\u306f\u305d\u306e\u3046\u3061DE10 nano\u3092\u8cb7\u3046\u304b\u3082\u3057\u308c\u306a\u3044\uff0e \u306a\u304a,\u3053\u3053\u306b\u3042\u308b\u60c5\u5831\u306f2017\u5e744\u670824\u65e5\u6642\u70b9\u306e\u3082\u306e\u3067\u3042\u308a,\u53e4\u304f\u306a\u3063\u3066\u4f7f\u3048\u306a\u304f […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[5],"tags":[],"class_list":["post-140","post","type-post","status-publish","format-standard","hentry","category-tech"],"_links":{"self":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts\/140","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/comments?post=140"}],"version-history":[{"count":0,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/posts\/140\/revisions"}],"wp:attachment":[{"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/media?parent=140"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/categories?post=140"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/p-0.me\/b\/wp-json\/wp\/v2\/tags?post=140"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}